1. Field of the Invention
The present invention is directed to memory devices and, more particularly, to methods and circuits for reading information into and out of a memory device.
2. Description of the Background
Computer designers are continually searching for faster memory devices that will permit the design of faster computers. A significant limitation on a computer's operating speed is the time required to transfer data between a processor and a memory circuit, such as a read or write data transfer. Memory devices such as dynamic random access memories (DRAMs), synchronous dynamic random access memories (SDRAMs), flash memories, etc. typically include a large number of memory cells arranged in one or more arrays, each array comprised of rows and columns. Each memory cell provides a location at which the processor can store and retrieve one bit of data, sometimes referred to as a memory bit or m-bit. The more quickly the processor can access the data within the memory cells, the more quickly it can perform a calculation or execute a program using the data.
FIG. 1 shows, in part, a typical computer system architecture. A central processing unit (CPU) or processor 10 is connected to a processor bus 12, which in turn is connected to a system or memory controller 14. The memory controller 14 may be connected to an expansion bus 16. The memory controller 14 serves as interface circuitry between the processor 10 and a memory device 18. The processor 10 issues a command and an address which are received and translated by the memory controller 14. The memory controller 14 applies the translated command signals on a plurality of command lines 20 and the translated address on a plurality of address lines 22 to the memory device  18. These command signals are well known in the art and include, in the case of a DRAM, RAS (row address strobe), CAS (column address strobe), WE (write enable) and OE (output enable), among others. A clock signal is also provided on CLK lines 24. Corresponding to the processor-issued command and address, data is transferred between the controller 14 and the memory 18 via datapath lines 26.
Methods exist to enable memory devices, such as DRAM memory 18, to appear to external devices to be operating faster than the time it takes for the memory device to retrieve data from the array. These methods include pipeline and prefetch methods of operation. The pipeline method divides internal processing into a number of stages and sequentially processes information relating to one unit of data through each stage. Processing in each stage is carried out simultaneously in parallel, such that the rate at which data can be output from the device can be greater than the rate at which data is retrieved from the array. In the prefetch method, all internal processing is carried out in parallel, and parallel to serial conversion is performed at the input/output section.
Both the pipeline and prefetch methods can be used to support, for example, a burst mode of operation. The burst mode of operation is a mode of operation in which the starting address for a data string is provided to the memory device. The data string to be read out of the memory or written into the memory is then synchronously output or input, respectively, with a clock signal.
Historically, synchronous DRAMs have supported both an interleaved and a sequential burst mode of operation. Advance DRAM technology standards are being defined with an 8-bit external prefetch and capability to support a 4-bit or 8-bit internal prefetch. With a 4 -bit internal prefetch, the sequential read or write crosses a boundary and is therefore difficult to implement as illustrated by the following table, Table 1.
TABLE 1StartingInternal BitsInternal BitsAddress[0 1 2 3][4 5 6 7]00 1 2 34 5 6 711 2 3 45 6 7 022 3 4 56 7 0 133 4 5 67 0 1 244 5 6 70 1 2 355 6 7 01 2 3 466 7 0 12 3 4 577 0 1 23 4 5 6
As seen from Table 1, except for starting addresses 0 and 4, the sequential burst cannot be executed without an 8-bit internal burst, adding cost, or a dual prefetching, which adds latency.
The existing interleave burst mode supports a 4-bit internal prefetch but some applications still use a sequential type of access burst mode. One solution is to always start the read burst at index 0 and sequence through the data. That solution is acceptable only when the word stored at index 0 is the next critical word. If the critical word is indexed at any other location, latency is introduced.
Thus, the need exists for a method and apparatus for enabling both 8-bit and 4-bit internal prefetches for new architectures without adding cost or latency to the new architecture.